Eshylon MESCs overcome this limitation, enabling dramatic ROI through reuse of mm or mm tool sets for smaller substrates bonded to Eshylon carriers. Thin Wafer Handling. With mobile devices forcing miniaturization of packaged ICs, device thickness must be reduced dramatically. Backside thinning of ultra-thin and delicate substrates presents serious wafer handling challenges that Eshylon solves.
Good bye breakage, low yields and slow throughput.
The Next Generation of Temporary Wafer Bonding
Wafer Thinning and CMP. Traditionally, wafers are bonded to a handle carrier with chemical bonding agents or tapes for backside thinning.
Both processes present release difficulties when the wafer it at its most valuable state. Once these processes are complete, the thin wafer can be easily removed in seconds. We add a final bonding surface that is slightly conformal for bonding bumped surfaces. Instant, delicate release with no intermediate agents.
Layer transfer processes and engineered substrates are enabling technologies for logic scaling by helping to deliver significant improvements in device performance, functionality and power consumption. Direct wafer bonding with plasma activation is a proven solution for enabling heterogeneous integration of different materials, high-quality engineered substrates as well as thin-silicon layer transfer applications. Since then, we have continuously enhanced the performance and CoO of our direct bonding platforms to help our customers bring the benefits of engineered substrates to a wider range of applications.
Capable of processing both mm and mm wafers, the system ensures a void-free, high-throughput, and high-yield production process.
EV Group EVG is a leading supplier of equipment and process solutions for the manufacture of semiconductors, microelectromechanical systems MEMS , compound semiconductors, power devices and nanotechnology devices. Founded in , EV Group services and supports an elaborate network of global customers and partners all over the world. The procedural steps of anodic bonding are divided into the following: . Differing coefficients of thermal expansion pose challenges for anodic bonding.
Excessive mismatch can harm the bond through intrinsic material tensions and cause disruptions in the bonding materials. The use of sodium-containing glasses, e. Borofloat or Pyrex, serve to reduce the mismatch. Anodic bonding is first mentioned by Wallis and Pomerantz in This method is used up to date as encapsulation of sensors with electrically conducted glasses. The anodic bonding procedure is able to bond hydrophilic and hydrophobic silicon surfaces equally effectively. The glass wafer can also be chemically etched or powder blasted for creating small cavities, where MEMS devices can be accommodated.
Further mechanisms supporting the bonding process of not completely inert anodic materials can be the planarization or polishing of surfaces and the ablation of the surface layer by electrochemical etching. The wafers that meet the requirements are put into atomic contact.
As soon as contact is first established, the bonding process starts close to the cathode and spreads in fronts to the edges, the process taking several minutes. An electrode is in contact with the glass wafer either through a needle or a full area cathode electrode.
If using a needle electrode, the bond spreads radially to the outside which makes it impossible to trap air between the surfaces.
The radius of the bonded area is approximately proportional to the square root of time elapsed during the procedure. The use of a full area cathode electrode shows bond reactions over the whole interface after powering up the potential. That results, combined with humidity in formation of NaOH. High voltage helps to support the drifting of the positive ions in glass to the cathode. The diffusion is according to the Boltzmann distribution exponentially related to the temperature. Silicon is unlike, e.
Bonding - Axus Technology
In result no ions drift out of the silicon into the glass during the bond process. This affects a positive volume charge in the silicon wafer on the opposite side. In the gap between silicon and glass the bond voltage drops. The bond process as a combination of electrostatic and electrochemical process starts.
The electrical field intensity in the depletion region is so high that the oxygen ions drift to the bond interface and pass out to react with the silicon to form SiO 2 compare to figure "ion drifting in bond glass" 2. Based on the high field intensity in the depletion region or in the gap at the interface, both wafer surfaces are pressed together at a specific bond voltage and bond temperature. Typically, the bonding or sealing time becomes longer when temperature and voltage are reduced.
The thin formed oxide layer between the bond surfaces, siloxane Si-O-Si , ensures the irreversible connection between the bonding partners. After the bonding process, slow cooling over several minutes has to take place. This can be supported by purging with an inert gas. The cooling time depends on the difference of CTE for the bonded materials: the higher the CTE difference, the longer the cooling period.
From Wikipedia, the free encyclopedia.
- Applications and Technology.
- A Model for the Silicon Wafer Bonding Process - IOPscience.
- What is Wafer Bonding?.
- Covalent bonding enables wafer-level packaging and heterogeneous integration?
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Wallis; D. Pomerantz Journal of Applied Physics. Archived from the original on