Figure 2A is a schematic diagram illustrating a cross-sectional side-view diagram of a multi-fin FinFET transistor formed within a portion of an integrated circuit chip.
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Figure 2B is a schematic diagram of the same structure from a top-view perspective. The schematic diagrams illustrate a substrate 30, an oxide 31, multiple fins 32, an insulator material 60, and a gate conductor 90 formed over the fins 32 and insulator As can be seen more clearly with respect to the perspective diagram in Figure 1 , the fins 32 shown in Figure 2 A extend into and out of the page and include source and drain regions 4 at their ends.
As shown in Figure 2B , the gate 90 runs perpendicular to the fins 32 and crosses the channel regions 24 of each of the fins As shown in Figure 2A , the preferred embodiment of the present invention can use more than one fin per single FinFET. As shown in Figure 2B , all the sources and drains of the different fins are electrically connected to external wiring 25 so that all of the fins 32 act together when gating the conductivity between the sources and drains.
By using multiple fins, the circuit designer can increase or decrease the channel area 24 that is exposed to, but insulated from the gate. Therefore, for fins having the same length and height, two fins would double the effective channel width when compared to a single fin, three fins would triple the effective channel width, etc.
Further, by providing the designer with the ability to use fins of different heights within a single transistor, the preferred embodiment of the present invention allows a finer granularity of channel surface area change, thereby allowing finer tuning resolution between the different circuits within a chip. Figures illustrate one method utilized by preferred embodiments of the present invention by showing various manufacturing stages of the inventive structure.
More specifically, Figure 3 illustrates the use of an SOI wafer having an active e. Item 33 represents a silicon dioxide layer in one embodiment. In another embodiment, item 33 represents a silicon dioxide with an overlying polysilicon layer. Item 34 represents a silicon nitride layer formed over the layer In Figure 4 , a photoresist 40 is formed and patterned over the silicon nitride layer The structure is then etched to remove the exposed portions 41 of the structure down to the active silicon layer Next, as shown in Figure 5 , the structure is subjected to a high temperature oxidation process.
This oxidation process consumes a portion of the active silicon 32 that is exposed through the opening 41 in the resist. The photoresist 40 is then removed. As shown in Figure 5 , this reduces the height of the active silicon 32 in the selected region While the height of the active silicon region 32 could be reduced by continuing the etching process discussed above with respect to Figure 4 , the oxidation process produces a much higher level of control over the height reduction in the exposed area In Figure 6 , the nitride 34 is stripped using a selective removal process.
In addition, if layer 33 included a polysilicon component, the polysilicon could also be selectively removed at this stage.
A mask material 60 is then applied and patterned in locations where the fins are to be formed. In Figure 7 , the oxide is etched in a selective etching process that does not affect the underlying silicon Then, as shown in Figure 8 , mask material 60 is stripped and the areas of the silicon 32 that are not protected by the oxide 33 are selectively etched with respect to the oxide 31 to form the fins Fins 80 are formed in region 41 where the height of the silicon 32 was reduced in the oxidation process discussed above with respect to Figure 5 while fins 81 or formed in areas where the height of the active silicon 32 was not reduced.
Therefore, fins 80 have a reduced height when compared to fins In Figure 9 , the conductive gate material 90 is deposited and patterned. In addition, as is known in the FinFET art field, additional processing occurs to complete the transistors. For example, the regions of the fins extending beyond the gate material 4 are doped to create source and drain regions; insulator layers are formed, contacts are formed to the gate, source, and drain, etc. In this example, three transistors are formed.
While in Fig. Figure 10 is a flow diagram which shows an embodiment of the invention. In item , the preferred embodiment of the present invention employs, but is not limited to, an SOI wafer as the starting point. Next, in item , the preferred embodiment of the present invention forms an oxide layer on the active silicon layer. Then, in item , the preferred embodiment of the present invention patterns a mask, or masking layers, above the oxide layer.
In item , the preferred embodiment of the present invention performs a thermal oxidation to reduce the height of regions of the active silicon layer not protected by the mask. In item , the preferred embodiment of the present invention removes the mask, or masking layer. Next, in item , the preferred embodiment of the present invention patterns a second mask over the oxide and active silicon layer. In item , the preferred embodiment of the present invention patterns the active silicon layer into fins.
The preferred embodiment of the present invention then forms gate oxides over channel regions of the fins in item In item , the preferred embodiment of the present invention patterns gate conductors over the fins so that the gate conductors cross channel regions of the fins.
FinFETs and Other Multi-Gate Transistors
Lastly, in item , the preferred embodiment of the present invention dopes portions of the fins not covered by the gate conductor to form source and drain regions in the fins. As shown above, the preferred embodiment of the present invention provides individual control over the height of the fins of different FinFET devices within a given chip to allow tuning of the channel widths to achieve a certain performance goal, and in addition, the preferred embodiment of the present invention provides the following methodology regarding the selection of different fin heights.
The forgoing description includes a single high temperature oxidation process to reduce the height of a selected portion of the active silicon that will be patterned into the fins. This process could be repeated a number of different times using different masks to create three or more different fin heights as opposed to the two fin heights discussed above.
However the preferred embodiment of the present invention limits the need to perform a large number of high temperature oxidation processes by utilizing the fin height ratios discussed below. This methodology limits the fin heights and associated channel widths to multiples quanta of a base fin height to simplify processing and allow designers the broadest range of channel width choices while maintaining reasonable manufacturing process steps.
The fins can be spaced at a frequency no greater than approximately the lithography scale e. Taller fins would give higher current density per unit area because fewer fins would have to be utilized to achieve a desired channel width; however, this would be at the expense of larger channel width steps coarser granularity. Smaller fins will allow finer granularity of channel widths; however, this would consume an excessive amount of chip real-estate.
Through experimentation, the inventors have determined that this ratio produces optimal design solution results. This solution allows a single high temperature oxidation process to be utilized thereby maintaining high yield. To the contrary, if some fins were made dramatically smaller than others, special processes would have to be utilized to form the contacts, source, drain, oxide, etc. In transistor 91, the channel width is equal to one which, as discussed above, it is actually two times the height of the fins.
Therefore, as shown above, the preferred embodiment of the present invention allows FinFET devices to be tuned according to a circuit designer's needs through the use of multiple fins that can have different heights. The finer granularity of channel width thus enabled allows those circuits whose operation is critically dependent on the relative drive strengths, or performance, of the transistors within, to occupy less physical area than would otherwise be possible.
Furthermore, narrower total channel width can be achieved in these circuits, thereby resulting in lower power dissipation of the resulting circuits, when compared to conventional structures. While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practised with many modifications while remaining within the scope of the appended claims.
The invention is useful in the field of semiconductor devices, and more particularly devices comprising field effect transistors. A method of manufacturing a FinFET device, the method comprising: forming a bottom oxide on a silicon substrate ;. The method of claim 1, wherein said patterning of said active silicon layer comprises: patterning a second mask over said active silicon layer; and. The method of claim 1 or claim 2, further comprising patterning a gate conductor over said fins such that said gate conductor crosses channel regions of said fins USB2 en.
EPB1 en. KRB1 en. CNC en. ATT en. DED1 en. TWIB en. WOA2 en. Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication. Varying carrier mobility in semiconductor devices to achieve overall design goals. Three dimensional CMOS field effect transistor and method of fabricating the same. Fin field effect transistor arrangement and method of fabricating a fin field effect transistor arrangement. Independently accessed double-gate and tri-gate transistors in same process flow. USA1 en. Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby. CMOS devices with a single work function gate electrode and method of fabrication. Multiple device types including an inverted-T channel transistor and method therefor. Three-dimensional single transistor semiconductor memory device and methods for making same.
Electronic device including a fin-type transistor structure and a process for forming the electronic device. Method of forming a semiconductor device with decreased undercutting of semiconductor material. Process of forming an electronic device including a semiconductor island over an insulating layer. Methods of shaping vertical single crystal silicon walls and resulting structures.
Methods of fabricating intermediate semiconductor structures by selectively etching pockets of implanted silicon. Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure. Method for forming acute-angle spacer for non-orthogonal finfet and the resulting structure. Method of forming a multi-fin multi-gate field effect transistor with tailored drive current. Multi-gate non-planar field effect transistor structure and method of forming the structure using a dopant implant process to tune device drive current.
Method and structure for forming finFETs with multiple doping regions on a same chip. Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents. Systems and methods for a semiconductor structure having multiple semiconductor-device layers. Structure and method for effective device width adjustment in finFET devices using gate workfunction shift.
KRA en. Semiconductor device comprising finFETs fin Field Effect Transistors of different gate structures and method for fabricating the same. USB1 en. Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method.
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Fully-depleted, fully-inverted, short-length and vertical channel, dual-gate, cmos fet. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology. Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture. CNA en. EPA4 en. TWA en. WOA3 en. Contact seller.
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