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The basic cell C is extended generation procedures for bit-sliced microprocessors and re- to form two more general cells Ck and Ck.

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The internal lated devices. Bit slicing provides a structural regularity in the structure of C4,16 closely resembles that of the AMD processor system design which is known to facilitate fault diagnosis. The slice. Test sequences for these cells are derived in much the same way heuristic testing schemes used in practice do not guarantee as for C. It is shown that the test sequence for a single cell C, Ck, or complete fault detection [2], [3]. Furthermore, as is demon- Ck,n can easily be extended to a test sequence for an array of N strated here, they may yield far more tests than are necessary.

It is observed that for test generation purposes, bit-sliced microprocessors Our goal is to construct systematic test generation methods can be viewed as C-testable iterative logic arrays, which require a which yield test sequences that are complete and of near- constant number of test patterns independent of array size.


Some new minimal length. The second is avoided by testing the primitive compo- arrays, microprocessors, testability, test generation. Finally, the regular intercon- I. We show that bit-sliced microprocessors applied to digital systems containing LSI and VLSI compo- can be modeled in a natural way as iterative logic arrays that nents. Conventional testing methods have two serious limita- require a constant number of tests independent of array size; tions: 1 they only recognize low-level devices such as gates and such arrays have been called C-testable [10], where C stands flip-flops as primitive elements, and 2 they use low-level fault for constant.

In systems containing tens of thousands of gates and lines, the amount of computation required to A device U performing a set of operations on n-bit operands construct a comprehensive test set can be enormous. Fur- is said to be bit-sliced if a system that performs the same set thermore, a gate-level description of the system components of operations on Nn-bit operands can be constructed by in- may be unavailable to the test designers.

Manufacturers of terconnecting N copies of U in a regular way. The basic device devices such as microprocessors often only supply designers U is called a cell or slice, and the interconnection structure with register or function-level circuit diagrams. In a bit-sliced microprocessor, the cell U performs the functions of the arithmetic-logic unit ALU and the register file or scratchpad RAM of a computer. Manuscript received August 6, ; revised February 18, This paper was supported by the U.

The authors are with the Department of Electrical Engineering, University 4-bit microprocessor cell shown in Fig. Data output Fig. An array of 4-bit slices. Most commercial microprocessors are similar in general organization and functional capability to the [5], [6]. The Intel is unique in its use of a 2-bit slice with a separate bus for operand masking, and a separate main memory address register.

It also has right-shift logic which is implemented in the ALU itself, and no explicit left-shift logic.

1- Combinational Circuit Design SOP Implementation Part 2

The Texas In- struments 74S48 1 is a 4-bit slice having a double-length ac- cumulator and a dual memory address generator. It has only one other temporary storage register, hence any extra registers may have to be maintained externally. Another important Data output Status feature of the 74S48 1 is that it has built-in microprogrammed Carry lookahead Fig.

Digital system design with LSI bit-slice logic

Block diagram of the 4-bit microprocessor slice. The arithmetic operations operands of arbitrary length using the basic ILA cell inter- include addition, subtraction, and negation; while the logical connection structure. The two operands R and S can be obtained via the introduces structural simplicity and regularity in the connec- source multiplexer from several sources: an external input data tions between IC chips at the printed-circuit board level.

The final result of an operation performed by the arithme- and compactness in VLSI designs. For example, it is used ex- tic-logic circuits can be transferred to the scratchpad, the tensively in the design of the processor data path chip of the register T, or the output data line Y. Shift operations both Caltech OM-2 microcomputer [ 13].

The generates status eration model of bit-sliced processors. To allow arithmetic operations to processor cell model we make the following preliminary as- be extended to operands of arbitrary length, neighboring cells sumptions: communicate via carry borrow signals. Each cell generates 1 the operand size of the cell is one bit; a carry output signal CO which can be connected to the carry 2 the cell contains only two scratchpad registers, an ac- input line CI of the cell on its right.

This allows ripple carry cumulator A and one additional temporary register T; and propagation through the entire array. Similar left-shift and 3 only ripple-carry propagation is used between the cells right-shift connections between adjacent cells allow shift op- of a bit-sliced array. No communication The above assumptions may be justified as follows. The use between cells is needed by the logical operations. Further- cuits which produce two signals called carry generation G more, we will show that tests based on a 1-bit cell can easily and carry propagation P.

G and P are used to implement a be extended to larger cells. It is also worth noting that 1-bit scheme called carry lookahead which can be used in place of processors may be useful in themselves; the Motorola ripple carry propagation to speed up arithmetic operations. The use of only two ample, the [4], which generates from G and P the signals general-purpose registers is mainly to simplify the test gen- to be applied to the CI lines. Note, however, that if carry eration process. Again, direct extension of the model to cells lookahead is implemented, the microprocessor no longer has having a larger set of registers is possible, and is discussed later.

Ripple carry prop- agation only is allowed because, as noted earlier, carry look- ahead cannot be implemented without destroying the basic ILA structure. The OM-2 data path chip is also designed using 1-bit processor cells with ripple-carry interconnections. Commenting on this aspect of the OM-2 design, Mead and Conway [ 13, p. We will also consider increasing the number of scratchpad registers.

The basic 1-bit processor cell model C is shown in Fig. Apart from the foregoing assumptions, the cell structure and the functions of its component modules are similar to those of the and, indeed, of many commercially-available bit- sliced microprocessors. Shifting is performed in the shifter module ML. Also, to facilitate the microinstruction decoding process, we have distributed it among the various functional blocks; for example, the decoding logic for the lines 13, I4, and I5 that control the ALU function is included in the ALU module MF.

For example, components like multiplexers 0 1 0 D A f2 0 1 0 RminusS and registers are treated as primitive modules in our analysis. Corresponding to this functional view of primi- AO , R 3 S tive module behavior, we now define a fault model based on ALU source control ALU function control functional considerations. Let M be a primitive combinational or synchronous se- 17 16 Function 19 18 L output quential logic module in a circuit U under test.

To detect these faults, it is necessary prehensive fault detection using the checking sequence ap- and sufficient to apply all 2n input vectors to an n-input proach [8]. The clock circuitry is assumed to be fault-free and module. This fault model is relatively powerful. It includes as the clock lines are not shown explicitly.

This assumption is a proper subset all single and multiple faults of the standard widely used when analyzing faults in synchronous sequential stuck-line fault model. The restriction excluding sequential circuits. It is further assumed that only one module in the behavior appears to be relatively minor. This single fault assumption When M is a sequential circuit, we allow faults to cause any is included in most fault models.

It is justified if the module change in the state table of M that does not increase the failures are independent, and if U is tested frequently. This is quite realistic in the case of modules It should be emphasized that the foregoing model will only in which there are k binary memory elements and exactly 2k be applied to n-input s-state modules where n and s are rela- states; only sequential modules of this type will be considered.

The small size of the modules is necessary to make extend these eight tests to the corresponding members of TL, practical the essentially exhaustive testing methods required we need to define suitably all the other primary inputs of C. Although individual modules are tested The input D may be selected so that the desired F input re- exhaustively, networks of these modules are tested in an effi- quired in the next test for ML is generated.

The other primary cient nonexhaustive manner. These constant values are chosen to permit the signal IV. One way of doing In this section we show how to generate tests for the cell e this is to write signal L into the register A by setting I6 and I7 model C developed in the previous section using our functional to 0.

The contents of regi-ster A can then be propagated to Y fault model. A similar sequence of eight tests can be derived for each of the other three combinations of I8 and Ig. Hence, Mi allowed by the fault model. In it is necessary and sufficient for Ti to be the set of all 2n inputs a similar way it can be shown that the other combinational to the module, where n is the number of primary input lines of Mi. If Mi is a synchronous sequential circuit, then the modules MR, Ms, and MF can be tested completely by a combined test sequence T7 of length 66 [9].

Thus, no more checking sequence approach is used in constructing the se- than 98 test patterns are necessary to test all the combinational quence Ti [8]. This approach is found to yield minimal or modules of C. Smith "The prospects of multivalued logic technology substractor. Antoniou "low power dissipation MOS proposed scheme 15 T-gates are required without encoder.

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Here with the Vol. Sc no-5, P. Etiemble " Some new results for ternary compared with [3][5][10].


Table 8 gives average circuits"". IEEE journal on solid state circuits Vol. Table 8:Propagation-delay comparison 8 T. Kameyama "Synthesis of optimal T-gate networks in multiple valued logic" Proc. Yeoli "Logical on electronic computers. EC February Yang"Aminimization algorithm for ternary switching functions"Proc.

ISMVL Conclusion 14 I. IEE, Vol. The scheme based on improved Engineering"McGrawHill, Motorola series in solid ternary logic gate is also described. It exhibits significant state electronics. Thus it 17 T. Hanyu, M. The ternary logic functions can also be implemented using ternary PLAs [17] thereby increasing packing density, more complex function implementation etc. References 1 D. IEE Vol. Related Papers. Introduction: For applications where the gene- ral purpose microprocessors are not fast enough or do not have a desired instruction or set of instructions, bit slice processors are used to custom build a "dedicated" CPU.

The starting block or slice, is a 4- or 8-bit ALU with some registers and multiplex circuitry. The basic bit slices are connected in parallel to handle wider words. To perform useful operations, the bit sli- ce is told every little step what to perform, the microinstructions, stored in a ROM. Computer operation: A computer performing di- stributed control "moves" through a sequence of states in order to manipulate data and control the actual action of manipulation.

Complicated interlocking alarm systems in process industry are highly requiring such a kind of sequential machines. This paper deals mainly with the micro- programmed based sequence control. The control strategy and the data processing through such a system is shown in fig. If the system will be allowed to make decisions by its own the next action will be a function of the present state and conditional branch action is needed. The second approach is more flexible and is adopted only if the control sig- nal sequence. The control sequence is an inner computer itself. The inner computer is "microprogrammed" by "microinstructi- ons" forming a "microprogrammed control".

Microprogrammed Structures in LSI Architectures: The microprogrammed structures in LSI circu- its have followedtwo philosophies: - the first allowed manufacturers of LSI to fa- bricate the inner and the outer computer with the microprogrammed control built - in the chip; all decisions are obviously left to the manufacturer only. These are the commonly known to us micro- processors. The nameof these microprocessor is bit-slice ones.

The user can select registers and control of data flow and e- mulate any kind of known or new microprocessor family by changing microprogramming. Bit-slice microprocessors are fabricated by bi-polar technology and out-perform their MOS counterparts in speed at the penalty of greater dissipation. The instruction register: The instruction re- gister contains the outer computer instructions, that are treated as subroutines by the inner com- puter with the operation code as subroutine name and the operands as the argument of the subrouti- ne.

Bit-slice architecture: Fig. The outer computer consists of the main memory, the ALU, the instruction register a set of general registers including the condi- tion code one , the data and address buses and the inner computer. The inner computer has the microprogram store, the microinstruction register and the logic of "next address" generation. In the both formatsthe next address address is generated by the corresponding logic. ALU and Registers: The word length is defined on the basis that the ALU and the registers are built on a vertical slice basis and any word len- gth can be formed putting bit-slices side-by-side.

The Intel is a 2 bit slice and the AMD is a 4 bit slice. The ports are characterized by the field width and the control functions; to de- code it a combonational logic and multiplexing is used. The main memory: We can use any type of memo- ry. The size of the memory is limited by the word length of the Memory Address Register, which by default is one of the general registers and it is of length equal to the data word length.

The address space needed for the application defines next address individuall defined control signals next address field 2 field 3 Fig.

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An essential feature of microprogram- ming is to enhance pipelining. In horizontal for- mats the individual bits of the microinstructions are exclusively ored to each other and therefore a longer microinstruction word is needed but the number of microinstructions are less and the num- ber of the parallel operations greater. We can use mixed for- mats in different modules of the same micropro- gram.

In mixed format microprogramming usually the vertical format store is used as a look-up table, where the address is the operation code of the outer computer and the data at this address is apointer to the program stored in the horizon- tally microprogrammed part.